Method of fabricating semiconductor devices

ABSTRACT

A method for increasing the removal rate of a photoresist layer used as an ion implant mask. The method includes performing a pre-treatment of a substrate, such as a plasma process, before forming the photoresist layer. The method can be applied to the fabrication of semiconductor devices for increasing the removal rate of the photoresist layer.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a method of fabricating semiconductordevices. More particularly, the present invention relates to a method offabricating semiconductor devices that can increase the efficiency ofremoving photoresist.

2. Description of the Related Art

Photolithography is one of the critical process for fabricatingintegrated circuits. The photoresist layer used in a photolithographicprocess must be completely removed after a dry etching operation, a wetetching operation or an ion implant process to prevent any residues fromaffecting subsequent processing operations.

However, property of photoresist varies with processing environment. Forexample, in an ion implant process, the surface of a photoresist layerwill be hardened by the ions so that the gas trapped in the photoresistduring photolithographic process is hardly to come out. In the laterashing process, the gas exposes and cause pollution of the wafer(popping). Moreover, after the ion implant process, an ashing treatmentwith CF₄ and an clean process using high-temperature RCA solution(developed by Kern and Puotinen in the experimental laboratory set up bythe Radio Corporation of America (RCA) in 1960) with dilute hydrofluoricacid (DHF), and now a commonly used wet cleaning solution) are performedto remove the surface-hardened photoresist. However, because thephotoresist is removed using an RCA solution with DHF raised to a hightemperature, upward of about 70° C., the process of removing thephotoresist will lead to a wasting of some oxide material on thesubstrate. Ultimately, the performance of the device may be affected.

To prevent the effect a high-temperature RCA solution on the performanceof a device, a low temperature RCA solution without DHF is widelyadopted to remove photoresist material after an ion implant process.Yet, the efficiency or removal rate of photoresist material using a lowtemperature RCA solution is rather low. Moreover, it is difficult toremove the photoresist material completely. Thus, the process forremoving photoresist material after an ion implant process needs toimprove.

SUMMARY OF THE INVENTION

Accordingly, the present invention is to provide a method of fabricatingsemiconductor devices that can increase the efficiency of removingphotoresist material after an ion implant process.

At least another objective of the present invention is to provide amethod of fabricating semiconductor device that can increase the processwindow for removing photoresist material.

To achieve these and other advantages and in accordance with the purposeof the invention, as embodied and broadly described herein, theinvention provides a method of fabricating semiconductor devices. Themethod includes forming a gate on a substrate and forming a lightlydoped source/drain region in the substrate thereafter. Then, spacers areformed on the respective sidewalls of the gate. After that, apre-treatment is performed on the exposed gate structure, spacers andsubstrate and then a patterned photoresist layer is formed on thesubstrate. Thereafter, using the patterned photoresist layer, the gatestructure and the spacers as a mask, an ion implant process is performedto form source/drain regions in the substrate. Finally, the patternedphotoresist layer is removed.

According to one embodiment of the present invention, the pre-treatmentincludes a plasma treatment, for example. The gases used in the plasmaprocess is selected from a group consisting of hydrogen, oxygen,nitrogen, nitrous oxide, water or their combination. The plasma processis carried out at a temperature between 100° C. to 260° C.

According to one embodiment of the present invention, after formingspacers on the sidewalls of the gate but before performing thepre-treatment process, further includes removing the polymer byproductsformed in the process of forming the spacers. Further, the patternedphotoresist layer is removed by using an ashing process and a cleaningprocess, wherein the ashing process without using CF₄ and the cleaningprocess using a cleaning solution without dilute hydrofluoric acid.

In the present invention, the pre-treatment before forming thephotoresist layer is able to prevent the formation of popping in thepatterned photoresist layer during or after the ashing process so thatthe procedure for cleaning the patterned photoresist layer can have ahigher process window and efficiency.

The present invention also provides a method for increasing the removalrate of a photoresist layer used as an ion implant mask. The methodincludes providing a substrate and performing a pre-treatment process onthe substrate before forming a photoresist layer.

According to one embodiment of the present invention, the pre-treatmentincludes a plasma treatment, for example. The gas used in the plasmaprocess is selected from a group consisting of hydrogen, oxygen,nitrogen, nitrous oxide, water or their combination. The plasma processis carried out at a temperature between 100° C. to 260° C.

In the present invention, a pre-treatment of the surface of a substrateis carried out before forming the photoresist pattern that serves as anion implant mask. The pre-treatment process can increase the efficiencyof removing photoresist material in a subsequent process.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a flow diagram showing the steps for fabricating asemiconductor device according to the present invention.

FIGS. 2A through 2C are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to the presentinvention.

FIG. 3 is a photo showing an example of the application of thepre-treatment process according to the present invention.

FIG. 4 is a photo showing another example of the application of thepre-treatment process according to the present invention.

FIG. 5 is a photo showing a comparison example without performing apre-treatment process.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Reference will now be made in detail to the present preferredembodiments of the invention, examples of which are illustrated in theaccompanying drawings. Wherever possible, the same reference numbers areused in the drawings and the description to refer to the same or likeparts.

FIG. 1 is a flow diagram showing the steps for fabricating asemiconductor device according to the present invention. As shown inFIG. 1, a substrate is provided in step 100. The substrate can be asilicon substrate or a structural component having logic devices ormemory devices such as a gate, a gate oxide layer or all kinds oflightly doped regions disposed thereon.

In step 102, a pre-treatment for the substrate is carried out. Thepre-treatment is a plasma treatment, for example. The gas used in theplasma treatment is selected from a group consisting of hydrogen,oxygen, nitrogen, nitrous oxide, water and their combination. The plasmatreatment is performed at a temperature between 100° C. to 260° C. Theplasma treatment can produce a buffer layer over the substrate so thatthe substrate is isolated from a subsequently formed photoresist layerand the efficiency of removing the photoresist material is substantiallyincreased.

In step 104, a patterned photoresist layer is formed over the substrate.Then, in step 106, using the patterned photoresist layer as a mask, anion implant process is carried out to form a doped region in thesubstrate. The doped region is a source/drain region, for example. Inthe presence of the buffer layer, the gas in the photoresist layer canbe channeled out through the buffer layer instead of being trappedduring ashing process. Hence, popping resulting from trapped gas can beavoided.

In step 108, the patterned photoresist layer is removed. The method ofremoving the patterned photoresist layer includes performing an ashingprocess using oxygen plasma without CF₄ and cleaning with an RCAsolution without DHF thereafter. The process of cleaning the substratewith an RCA solution without DHF after performing the ashing processincludes a two-step process, for example. First, a first cleaningoperation with a solution mixture containing ammonia, hydrogen peroxideand de-ionized water heated to a temperature between 20° C. to 30° C. iscarried out. This is followed by a second cleaning operation with asolution mixture containing hydrochloric acid, hydrogen peroxide andde-ionized water heated to a temperature between 20° C. to 30° C.

In the present invention, a pre-treatment is carried out before formingthe patterned photoresist layer. This prevents popping from ashingprocess after the ion implant process and increases the process windowand efficiency in removing the patterned photoresist layer.

FIGS. 2A through 2C are schematic cross-sectional views showing thesteps for fabricating a semiconductor device according to the presentinvention. The semiconductor device is a MOS device, for example. Asshown in FIG. 2A, a substrate 200 having isolation structures 201 formedthereon is provided. Then, a gate oxide layer 202 and a gate 204 areformed over the substrate 200. The gate oxide layer 220 is a siliconoxide formed by performing a thermal oxidation process, for example. Thegate 204 is a polysilicon layer formed, for example, by performing alow-pressure chemical vapor deposition (LPCVD) process, for example.Thereafter, off-set spacers 205 are formed on the respective sidewallsof the gate 204. The off-set spacers 205 are formed, for example, byperforming a chemical vapor deposition process to form a dielectriclayer over the substrate 200 and performing an anisotropic etchingprocess to etch back the dielectric layer. After that, ahigh-temperature thin oxide annealing treatment is carried out toeliminate the crystalline defects formed in the gate 204 and on thesurface of the substrate 200. Then, a pair of lightly doped source/drainregions 206 is formed in the substrate 200. The lightly dopedsource/drain regions 206 is an N-type lightly doped region or P-typelightly doped region formed, for example, by performing an ion implantprocess 209 using a patterned photoresist layer 207 as a mask.

Thereafter, the patterned photoresist layer 207 is removed. The methodof removing the patterned photoresist layer 207 includes, for example,removing most of the patterned photoresist layer 207 with oxygen plasmaand then removing the remaining patterned photoresist layer 207 using alow temperature RCA cleaning process. The low temperature RCA cleaningprocess includes performing a cleaning operation using a solutionmixture containing ammonium hydroxide, hydrogen peroxide and de-ionizedwater at a temperature between 20° C. to 30° C. Then, another cleaningoperation is performed using a solution mixture containing hydrochloricacid, hydrogen peroxide and de-ionized water at a temperature between20° C. to 30° C.

As shown in FIG. 2B, spacers 208 are formed on the respective sidewallsof the gate 204. The spacers 208 are formed by depositing silicon oxideor silicon nitride to form a silicon oxide or a silicon nitride layer ordepositing silicon oxide and silicon nitride in sequence to form anoxide/nitride composite layer. Then, an anisotropic etching process iscarried out until the gate 204 and a portion of the substrate 200 isexposed. The anisotropic etching process will result in the productionof some polymer. Thereafter, a cleaning operation is carried out toremove the polymer formed in the process of forming the spacers 208. Thecleaning operation is a cleaning process using an RCA solution withoutDHF, for example. The RCA cleaning operation includes performing acleaning operation using a solution mixture containing ammoniumhydroxide, hydrogen peroxide and de-ionized water at a temperaturebetween 70° C. to 80° C. Then, another cleaning operation is performedusing a solution mixture containing hydrochloric acid, hydrogen peroxideand de-ionized water at a temperature between 70° C. to 80° C.

After that, a pre-treatment is performed on the exposed gate 204, thespacers 208 and the substrate 200. The pre-treatment is a plasmaprocess, for example. The gas used in the plasma process is selectedfrom a group consisting of hydrogen, oxygen, nitrogen, nitrous oxide,water and their combination. The pre-treatment is carried out at atemperature between 100° C. to 260° C. After performing the plasmaprocess, an invisible buffer layer (not shown) is formed on thesubstrate 200. Hence, the substrate 200 and a subsequently formedphotoresist layer are isolated so that the efficiency of removing thephotoresist layer can be increased.

Thereafter, a patterned photoresist layer 210 is formed over thesubstrate 200. The patterned photoresist layer 210 exposes the gate 204,the lightly doped source/drain regions 206 and the spacers 208. Then,using the patterned photoresist layer 210, the gate 204 and the spacers208 as a mask, a pair of source/drain regions 212 is formed in thesubstrate 200. The source/drain regions 212 are N-type heavily dopedregions or P-type heavily doped regions formed, for example, byperforming an ion implant process 214.

The photoresist layer 210 is removed, for example, by applying oxygenplasma and then performing a low temperature RCA cleaning process toform the MOS device structure as shown in FIG. 2C. The low temperatureRCA cleaning process is identical to the aforementioned low temperatureRCA cleaning process so that a detailed description is omitted.

As a first example, a shallow trench isolation (STI) structure is formedon a substrate. Then, a get oxide, gate and spacers are formed on thesubstrate. The height and depth of the STI structure on the substrateand the thickness of the spacers are measured. Thereafter, apre-treatment process is carried out using hydrogen and nitrogen plasmaat a temperature between 100° C. to 260° C. After that, the remainedoxide above the substrate and depth of the STI structure on thesubstrate and the thickness of the spacers are again measured. Theresults are listed in Table 1. Then, a patterned photoresist layer isformed. Using the patterned photoresist layer as a mask, an ion implantprocess is performed to form doped regions in the substrate. Then, thesubstrate is cleaned using an ashing without CF₄ and an RCA without DHFcleaning solution at room temperature to remove the patternedphotoresist layer. A photo of the resulting substrate is shown in FIG.3.

In a second example, the method is identical to the first example exceptthat the pre-treatment is carried out using oxygen plasma at atemperature between 100° C. to 260° C. The results are also listed inTable 1 and a photo of the resulting substrate is shown in FIG. 4.

TABLE 1 Example 1 Example 2 Before pre- After pre- Before pre- Afterpre- treatment treatment treatment treatment Remained 28.09 Å 28.38 Å26.56 Å 25.36 Å oxide above the substrate Depth of the 3566.4 Å 3560.2 Å3515.7 Å 3519.3 Å STI Width of the 0.17941 μm 0.17968 μm 0.18528 μm0.18483 μm spacers

According to the results shown in Table 1, the difference between thevalues measured before and after the pre-treatment process is within thetolerance range. This indicates that the pre-treatment process will notaffect the dimension of various components on the surface of the MOStransistor. Furthermore, no photoresist residues can be seen in theFIGS. 3 and 4 after deploying the method of the present invention.

In a comparison example 1, a method identical to the first example isused except that the ion implant process is carried out withoutperforming the pre-treatment described in the present invention. A photoof the substrate is shown in FIG. 5. As recognized in the photo, somephotoresist residues can be seen in the doped region.

According to the first example, the second example and the compareexample 1, the method in the present invention not only can removephotoresist residues completely, but can increase the removal rate ofthe photoresist layer used as an ion implant mask. In addition, thepre-treatment process before forming the patterned photoresist layerpermits the removal of photoresist using a low temperature cleaningsolution. Moreover, the photoresist material can be completely removedwithin a shorter period of time so that the process window is increased.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A method of fabricating a semiconductor device, comprising: providinga substrate; forming a gate on the substrate; forming a lightly dopedsource/drain region in the substrate; forming a spacer on the sidewallof the gate; performing a pre-treatment process on the gate, the spacerand the substrate; after performing the pre-treatment process, forming apatterned photoresist layer on the substrate; performing an ion implantprocess using the patterned photoresist layer, the gate and the spaceras a mask to form a source/drain region; and removing the patternedphotoresist layer.
 2. The method of claim 1, wherein the pre-treatmentprocess includes a plasma treatment.
 3. The method of claim 2, whereinthe gases used in the plasma treatment is selected from a groupconsisting of hydrogen, oxygen, nitrogen, nitrous oxide, water and theircombination.
 4. The method of claim 2, wherein the plasma treatment isperformed at a temperature between about 100° C. to 260° C.
 5. Themethod of claim 1, wherein the after forming the spacer on the sidewallof the gate, further includes performing a cleaning operation to removea polymer formed in the process of forming the spacer.
 6. The method ofclaim 5, wherein the pre-treatment process is performed after thecleaning operation but before forming the patterned photoresist layer.7. The method of claim 1, wherein the step of removing the patternedphotoresist layer comprises an ashing process and a cleaning processusing a cleaning solution.
 8. The method of claim 7, wherein the ashingprocess is performed without using CF₄.
 9. The method of claim 7,wherein the cleaning process is performed without dilute hydrofluoricacid.